qat.middleend.default module

class DefaultMiddleend(model, target_data=TargetData(max_shots=10000, default_shots=1000, QUBIT_DATA=QubitDescription(sample_time=1e-09, samples_per_clock_cycle=1, instruction_memory_size=50000, waveform_memory_size=1500, pulse_duration_min=6.4e-08, pulse_duration_max=0.001, pulse_channel_lo_freq_min=1000000, pulse_channel_lo_freq_max=10000000000, pulse_channel_if_freq_min=0, pulse_channel_if_freq_max=10000000000, passive_reset_time=0.001), RESONATOR_DATA=ResonatorDescription(sample_time=1e-09, samples_per_clock_cycle=1, instruction_memory_size=50000, waveform_memory_size=1500, pulse_duration_min=6.4e-08, pulse_duration_max=0.001, pulse_channel_lo_freq_min=1000000, pulse_channel_lo_freq_max=10000000000, pulse_channel_if_freq_min=0, pulse_channel_if_freq_max=10000000000)))

Bases: CustomMiddleend

The standard middle end used for antic pipelines.

Implements a number of passes, including validation and sanitisation of IR, and optimizations. Also implements a number of lowering passes, e.g., lowering repeats to more explicit control flow instructions.

Parameters:

• model (PhysicalHardwareModel) – The hardware model that holds calibrated information on the qubits on the QPU.

• clock_cycle – The period for a single sequencer clock cycle.

static build_pass_pipeline(model, target_data=TargetData(max_shots=10000, default_shots=1000, QUBIT_DATA=QubitDescription(sample_time=1e-09, samples_per_clock_cycle=1, instruction_memory_size=50000, waveform_memory_size=1500, pulse_duration_min=6.4e-08, pulse_duration_max=0.001, pulse_channel_lo_freq_min=1000000, pulse_channel_lo_freq_max=10000000000, pulse_channel_if_freq_min=0, pulse_channel_if_freq_max=10000000000, passive_reset_time=0.001), RESONATOR_DATA=ResonatorDescription(sample_time=1e-09, samples_per_clock_cycle=1, instruction_memory_size=50000, waveform_memory_size=1500, pulse_duration_min=6.4e-08, pulse_duration_max=0.001, pulse_channel_lo_freq_min=1000000, pulse_channel_lo_freq_max=10000000000, pulse_channel_if_freq_min=0, pulse_channel_if_freq_max=10000000000)))

Builds the default middle end pass pipeline. :type _sphinx_paramlinks_qat.middleend.default.DefaultMiddleend.build_pass_pipeline.model: PhysicalHardwareModel :param _sphinx_paramlinks_qat.middleend.default.DefaultMiddleend.build_pass_pipeline.model: The hardware model that holds calibrated information on the qubits on

the QPU.

Return type:

PassManager

Returns:

A PassManager containing a sequence of passes.

PydDefaultMiddleend

alias of DefaultMiddleend