qat.middleend.middleends module

class BaseMiddleend(model)

Bases: ABC

Base class for a middle end that takes an intermediate representation (IR) QatIR and alters it based on optimisation and/or validation passes.

Parameters:

model (None | QuantumHardwareModel) – The hardware model that holds calibrated information on the qubits on the QPU.

abstract emit(ir, res_mgr=None, met_mgr=None, compiler_config=None)

Converts an IR QatIR to an optimised IR. :type _sphinx_paramlinks_qat.middleend.middleends.BaseMiddleend.emit.ir: :param _sphinx_paramlinks_qat.middleend.middleends.BaseMiddleend.emit.ir: The intermediate representation. :type _sphinx_paramlinks_qat.middleend.middleends.BaseMiddleend.emit.res_mgr: Optional[ResultManager] :param _sphinx_paramlinks_qat.middleend.middleends.BaseMiddleend.emit.res_mgr: Collection of analysis results with caching and aggregation

capabilities, defaults to None.

Parameters:

• met_mgr (Optional[MetricsManager]) – Stores useful intermediary metrics that are generated during compilation, defaults to None.

• compiler_config (Optional[CompilerConfig]) – Compiler settings, defaults to None.

class CustomMiddleend(model, pipeline=None)

Bases: BaseMiddleend

Middle end that uses a custom pipeline to convert the IR to an (optimised) IR.

Parameters:

model (None | QuantumHardwareModel) – The hardware model that holds calibrated information on the qubits on the QPU.

emit(ir, res_mgr=None, met_mgr=None, compiler_config=None)

Converts an IR QatIR to an optimised IR with a custom pipeline. :type _sphinx_paramlinks_qat.middleend.middleends.CustomMiddleend.emit.ir: :param _sphinx_paramlinks_qat.middleend.middleends.CustomMiddleend.emit.ir: The intermediate representation. :type _sphinx_paramlinks_qat.middleend.middleends.CustomMiddleend.emit.res_mgr: Optional[ResultManager] :param _sphinx_paramlinks_qat.middleend.middleends.CustomMiddleend.emit.res_mgr: Collection of analysis results with caching and aggregation

capabilities, defaults to None.

Parameters:

• met_mgr (Optional[MetricsManager]) – Stores useful intermediary metrics that are generated during compilation, defaults to None.

• compiler_config (Optional[CompilerConfig]) – Compiler settings, defaults to None.

class DefaultMiddleend(model, clock_cycle=8e-09)

Bases: CustomMiddleend

Validates the compiler settings against the hardware model, finds calibrations within the IR, compresses contiguous PhaseShift instructions, checks that the PostProcessing instructions that follow an acquisition are suitable for the acquisition mode, validates that there are no mid-circuit measurements.

Parameters:

• model (QuantumHardwareModel) – The hardware model that holds calibrated information on the qubits on the QPU.

• clock_cycle (float) – The period for a single sequencer clock cycle.

static build_pass_pipeline(model, clock_cycle=8e-09)

Builds the default middle end pass pipeline. :type _sphinx_paramlinks_qat.middleend.middleends.DefaultMiddleend.build_pass_pipeline.model: :param _sphinx_paramlinks_qat.middleend.middleends.DefaultMiddleend.build_pass_pipeline.model: The hardware model that holds calibrated information on the qubits on

the QPU.

Return type:

PassManager

Returns:

A PassManager containing a sequence of passes.

class FallthroughMiddleend(model=None)

Bases: CustomMiddleend

A middle end that passes through an input InstructionBuilder and does not alter it.

Parameters:

model (None) – The hardware model that holds calibrated information on the qubits on the QPU.

class PydDefaultMiddleend(model)

Bases: CustomMiddleend

Parameters:

model (PhysicalHardwareModel) – The hardware model that holds calibrated information on the qubits on the QPU.

static build_pass_pipeline(model)

Return type:

PassManager